A semiconductor device, such as a flash memory, may include a gate structure for controlling a channel current and a source/drain doped region on both sides of the gate structure. The source/drain doped region is used for electrically connecting the interconnect layer in post-process through conductive plugs. Before forming the conductive plug, an interlayer dielectric layer is formed covering the gate structure and the source/drain doped region, followed by forming a contact hole in the interlayer dielectric layer. The contact hole is used for accommodating the conductive plug.
As the size between adjacent gate structures decreases, the size of the contact hole between the gate structures decreases, which are then limited by lithographic limitations. As such, a self-aligned contact hole process is used to have a protective layer on both the top surface and the sidewall surface of the gate structure and an interlayer dielectric layer covering the protective layer. A patterned photoresist layer is then formed on the interlayer dielectric layer. The patterned photoresist layer has an opening, and the opening has a size along the direction perpendicular to the sidewall of the gate structure larger than a distance between the adjacent gate structures. A contact hole is further formed in the interlayer dielectric layer between the adjacent gate structures by using the protective layer as a mask.
However, the semiconductor devices formed by conventional technologies have poor electrical performance. The disclosed semiconductor device and method are directed to solve one or more problems set forth above and other problems.